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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC2002/D
256KB and 512KB BurstRAMTM Secondary Cache Module for PowerPCTM - Based Systems
The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0 - PD2 are reserved for density and speed identification. * PowerPC-style Burst Counter on Board * Dual Readout SIMM for Circuit Density * Single 5 V 5% Power Supply * All Inputs and Outputs are TTL Compatible * Three State Outputs * Byte Parity * Byte Write Capability * Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz * Decoupling Capacitors for each Fast Static RAM * High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes * I/Os are 3.3 V Compatible
MPC2002 MPC2003
(Formerly MCM72MS32/64)
136-LEAD DIMM CASE 1104-01 TOP VIEW
1
34 35
68
BurstRAM is a trademark of Motorola. PowerPC and PowerPC 601 are trademarks of International Business Machines Corp.
5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MPC2002*MPC2003 1
PIN ASSIGNMENT 136-LEAD DIMM CASE 1104-01 TOP VIEW
PD2 VSS VSS VSS VSS
PD1 NC NC VSS VSS
PD0 NC VSS NC VSS
Cache Size 512KB 512KB 256KB 256KB
Module MPC2003SG66/60 MPC2003SG50 MPC2002SG66/60 MPC2002SG50
PD0 PD1 DQ0 DQ1 VCC DQ4 DQ6 DQP0 DQ8 DQ10 VSS K0 VSS DQ14 VCC DQ16 DQ17 DQ19 DQ21 VCC DQP2 DQ24 DQ26 DQ28 VSS DQ31 DQP3 VSS W0 W2 TSP BAA VCC W4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
VSS PD2 VCC DQ2 DQ3 DQ5 DQ7 VSS DQ9 DQ11 DQ12 VSS DQ13 DQ15 DQP1 VSS DQ18 DQ20 DQ22 DQ23 VSS DQ25 DQ27 DQ29 DQ30 VSS E0 W1 W3 G0 TSC VSS G1 W5
PIN NAMES
A0 - A15 . . . . . . . . . . . . . . . . . . . . . . Address Inputs K0, K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W0 - W7 . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write E0, E1 . . . . . . . . . . . . . . . . . . . . . . . . Module Enable G0, G1 . . . . . . . . . . . . . . . . . Module Output Enable DQ0 - DQ63 . . . . . . . . . . Cache Data Input/Output DQP0 - DQP7 . . . . . . . . . Data Parity Input/Output TSC . . . . . . . . . . . . . . . . . . Transfer Start Controller TSP . . . . . . . . . . . . . . . . . Transfer Start Processor BAA . . . . . . . . . . . . . . . . . . Burst Address Advance PD0 - PD2 . . . . . . . . . . . . . . . . . . Presence Detect VCC . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
W6 DQ32 DQ33 VSS DQ36 DQ38 DQ39 DQ40 VCC DQ43 DQ45 DQ46 DQP5 VSS K1 VSS DQ52 DQ53 DQ55 DQP6 VCC DQ58 DQ60 DQ62 DQP7 A0 A2 A4 A6 A8 A10 A12 A14 VSS
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
W7 E1 DQ34 DQ35 DQ37 VCC DQP4 DQ41 DQ42 DQ44 VSS DQ47 DQ48 DQ49 VSS DQ50 DQ51 DQ54 DQ56 VSS DQ57 DQ59 DQ61 DQ63 VCC A1 A3 A5 A7 NC A9 A11 A13 A15*
* This pin on the MPC2002 is a No Connect (NC)
MPC2002*MPC2003 2
MOTOROLA FAST SRAM
MPC2003 (64K x 72) MODULE BLOCK DIAGRAM
16 A0 - A15 TSP TSC BAA K0 G0 E0 MCM67M618 A0 - A15 LW 8 TSP TSC BAA K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17 DQ8 - DQ15 DQP1 DQ0 - DQ7 DQP0 W1
W0
MCM67M618 A0 - A15 LW 8 TSP TSC BAA K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17
W2 DQ16 - DQ23 DQP2 W3 DQ24 - DQ31 DQP3
MCM67M618 A0 - A15 LW 8 TSP TSC BAA K1 G1 E1 K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17
W4 DQ32 - DQ39 DQP4 W5 DQ40 - DQ47 DQP5
MCM67M618 A0 - A15 LW 8 TSP TSC BAA K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17
W6 DQ48 - DQ55 DQP6 W7 DQ56 - DQ63 DQP7
MOTOROLA FAST SRAM
MPC2002*MPC2003 3
MPC2002 (32K x 72) MODULE BLOCK DIAGRAM
A15 A0 - A14 TSP TSC BAA K0 G0 E0 15 NC MCM67M518 A0 - A14 LW 8 TSP TSC BAA K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17 DQ8 - DQ15 DQP1 DQ0 - DQ7 DQP0 W1 W0
MCM67M518 A0 - A14 LW 8 TSP TSC BAA K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17
W2 DQ16 - DQ23 DQP2 W3 DQ24 - DQ31 DQP3
MCM67M518 A0 - A14 LW 8 TSP TSC BAA K1 G1 E1 K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17
W4 DQ32 - DQ39 DQP4 W5 DQ40 - DQ47 DQP5
MCM67M518 A0 - A14 LW 8 TSP TSC BAA K G E DQ0 - DQ7 DQ8 UW 8 DQ9 - DQ16 DQ17
W6 DQ48 - DQ55 DQP6 W7 DQ56 - DQ63 DQP7
MPC2002*MPC2003 4
MOTOROLA FAST SRAM
BLOCK DIAGRAM (See Note)
BURST LOGIC BAA K Q1 BINARY COUNTER LOAD D1 D0 Q0 A0 64K x 18 MEMORY ARRAY INTERNAL ADDRESS 16
A1
TSC TSP
A1 EXTERNAL ADDRESS A15 - A0 ADDRESS REGISTERS
A0 A15 - A2
16
18 WRITE REGISTER
9
9
UW LW
DATA-IN REGISTERS
E
ENABLE REGISTER 9 9
OUTPUT BUFFER
G DQ0 - DQ8 DQ9 - DQ17 9 9
NOTE: All registers are positive-edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed using the new external address. Alternatively, a TSP-initiated two cycle WRITE can be performed by asserting TSP and a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE GRAPH. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE GRAPH (See Note)
0,0 A1, A0 = 1,1
0,1 1,0
NOTE: The external two values for A1 and A0 provide the starting point for the burst sequence graph. The burst logic advances A1 and A0 as shown above.
MOTOROLA FAST SRAM
MPC2002*MPC2003 5
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E H H L L L X X X X TSP L X L H H H H H H TSC X L X L L H H H H BAA X X X X X L L H H LW or UW X X X L H L H L H K L-H L-H L-H L-H L-H L-H L-H L-H L-H Address N/A N/A External Address External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Write Deselected G L X X I/O Status Data Out (DQ0 - DQ8) High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 6.0 - 10 to + 85 0 to +70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Storage Temperature Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MPC2002*MPC2003 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20.0 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20.0 ns) for I 20.0 mA.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH) AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA66 ICCA60 ICCA50 ISB1 VOL Min -- -- -- Max 1.0 1.0 1160 1100 1000 300 0.4 Unit A A mA
-- --
mA V
VOH 2.4 3.3 V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible PowerPC bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Input Capacitance (A0 - A15, TSP, TSC, BAA) (DQ0 - DQ63, DQP0 - DQP7) (Kx, Gx, Ex, Wx) Symbol Cin CI/O Cin Typ 25 8 12 Max 32 10 15 Unit pF pF pF
MOTOROLA FAST SRAM
MPC2002*MPC2003 7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5% TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) (W refers to either or both byte write enables)
MPC2002SG66/ MPC2003SG66 Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Select Address Address Status Data In Write Address Advance Chip Select Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tTSVKH tDVKH tWVKH tBAVKH tEVKH tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX Min 15 -- -- 6 3 0 2 -- 5 5 2.5 Max -- 9 5 -- -- -- 6 6 -- -- -- MPC2002SG60/ MPC2003SG60 Min 16.6 -- -- 6 3 0 2 -- 5 5 2.5 Max -- 11 5 -- -- -- 6 6 -- -- -- MPC2002SG50/ MPC2003SG50 Min 20 -- -- 6 3 0 2 -- 6 6 2.5 Max -- 14 6 -- -- -- 6 6 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 6 5 5 4 Notes
Hold Times:
0.5
--
0.5
--
0.5
--
ns
6
NOTES: 1. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high for the setup and hold times. 2. All read and write cycle timings are referenced from K or G. 3. G is a don't care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible PowerPC 60x external bus cycles. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device. 6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever TSP or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is selected.Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled.
AC TEST LOADS
+5V 480 OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF
Figure 1A
Figure 1B
MPC2002*MPC2003 8
MOTOROLA FAST SRAM
READ CYCLES
t KHKH
t KHTSX
K t KHKL t KLKH
t TSVKH
MOTOROLA FAST SRAM
t KHTSX t TSVKH t KHAX A1 t KHWX t WVKH A2 t KHEX t KHBAX t BAVKH t KHQV t GLQV (BAA SUSPENDS BURST) t GHQZ Q(A1) t KHQV t KHQX2 Q(A2) Q(A2 + 1) Q(A2 + 2) (BURST WRAPS AROUND TO ITS INITIAL STATE) Q(A2 + 3) Q(A2) Q(A2 + 1) t KHQZ SINGLE READ BURST READ
TSP
TSC
t AVKH
ADDRESS
LW, UW
t EVKH
E
BAA
G
t GLQX
DATA OUT
Q(A2 + 2)
MPC2002*MPC2003 9
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address.
WRITE CYCLES
t KHKH
K t KHKL t KHTSX t KLKH
MPC2002*MPC2003 10
t TSVKH t KHSX TSC STARTS NEW BURST t KHAX A1 W IS IGNORED FOR FIRST CYCLE WHEN TSP INITIATES BURST A2 A3 t WVKH t KHWX t KHEX t BAVKH BAA SUSPENDS BURST t DVKH D(A1) t GHQZ D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) t KHDX SINGLE WRITE BURST WRITE (WITH A SUSPENDED CYCLE) NEW BURST WRITE
t TSVKH
TSP
TSC
t AVKH
A
LW, UW
t EVKH
E t KHBAX
BAA
G
D
D(A3 + 2)
Q
Q(An - 1)
Q(An)
MOTOROLA FAST SRAM
BURST READ
COMBINATION READ/WRITE CYCLE (E low, TSC high)
tKHKH
K tKHKL tKLKH
tTSVKH TSP
tKHTSX
tAVKH ADDRESS A1
tKHAX A2 A3
tWVKH LW, UW
tKHWX
tBAVKH BAA
tKHBAX
G tDVKH D(A2) tKHQX1 tGHQZ tGLQX tKHQX2 tKHDX tGLQV
tKHQV DATA IN
DATA OUT
Q(A1)
Q(A3)
Q(A3 + 1)
Q(A3 + 2)
READ
WRITE
BURST READ
MOTOROLA FAST SRAM
MPC2002*MPC2003 11
APPLICATION EXAMPLE
DATA BUS DATA ADDRESS BUS ADDRESS CLOCK
MPC601 (PowerPCTM) BCLK K
ADDR CACHE CONTROL LOGIC
ADDR DATA K0 K1 TSC Wx MCM67M618FN9 G0 G1 TSP BAA MPC2003SG66
TS CONTROL
512K Byte Burstable, Secondary Cache Using MPC2003SG66 with a 66 MHz MPC601 PowerPCTM Figure 2
ORDERING INFORMATION
(Order by Full Part Number) MPC2002 MCM MPC2003
Motorola Memory Prefix Part Number
XX
XX
Speed (66 = 66 MHz, 60 = 60 MHz, 50 = 50 MHz) Package (SG = Gold Pad SIMM)
Full Part Numbers -- MPC2002SG66 MPC2003SG66
MPC2002SG60 MPC2003SG60
MPC2002SG50 MPC2003SG50
MPC2002*MPC2003 12
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
136-LEAD DIMM CASE 1104-01
A 0.006 (0.15) M T Y X U
S
C
NOTE 4
B
2X
N
-YVIEW AA
102
103
COMPONENT AREA
BACK VIEW
136
69
2X 2X
W
R
T
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
EEEEEEEEEEEE E EEEEEEEEEEEE E EEEEEEEEEEEE E EEEEEEEEEEEE E
COMPONENT AREA 34 35 R
Y
P
S
NOTE 4
-X-
68
1
V
NOTE 5
2X
L
2X
F
FRONT VIEW
J -TSIDE VIEW
NOTE 6
CCCCCCCCCCCC C CCCCCCCCCCCC C CCCCCCCCCCCC C CCCCCCCCCCCC C
W
2X
0.012 (0.30)
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND S DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION V DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. DIM A B C D F G H J K L M N P Q R S T U V W Y INCHES MIN MAX 4.045 4.055 0.995 1.005 --- 0.413 0.040 0.042 0.125 BSC 0.050 BSC --- 0.010 0.046 0.054 0.100 --- 1.650 BSC 0.075 0.085 0.400 BSC 0.125 --- 0.123 0.127 0.245 0.255 0.157 --- 0.064 0.060 3.784 BSC --- 0.236 0.062 --- 0.060 0.064 MILLIMETERS MIN MAX 102.74 103.00 25.27 25.53 --- 10.50 1.02 1.07 3.18 BSC 1.27 BSC --- 0.25 1.17 1.37 2.54 --- 41.91 BSC 1.91 2.16 10.16 BSC 3.18 --- 3.12 3.22 6.22 6.48 4.00 --- 1.52 1.63 96.11 BSC --- 6.00 1.57 --- 1.52 1.63
Q 0.006 (0.15)
M
TYX
L
M
VIEW AA
132X
G
CCC CC C CCC CC C CCC CC C CCC CC C
R
EE EE EE
136X
D 0.004 (0.10)
L
TYX
S
136X
K
136X
H
MPC2002*MPC2003 13
Literature Distribution Centers: USA/Europe: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MPC2002*MPC2003 14
*MPC2002/D*
MPC2002/D MOTOROLA FAST SRAM

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